1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and the semiconductor device, and more particularly to a method for manufacturing a semiconductor device having an element isolation film formed by the LOCOS (Local Oxidation of Silicon) technique.
2. Description of the Related Art
In the field of the method for manufacturing a semiconductor device, the "PBL" (Poly-Buffered LOCOS) technique is known as a method used for forming an element isolation film through the LOCOS technique. The element isolation film isolates various semiconductor devices such as MOS transistors. The PBL technique is to form a polycrystalline silicon (hereinafter referred to as "poly-Si") film previously, which serves as a buffer layer between an oxidation-resisting film and a semiconductor substrate. Specifically, this technique comprises the steps of previously forming an insulating film (pad oxide film) on the entire surface of a substrate, forming a poly-Si film constituting a pad poly-Si film (hereinafter referred to as "pad poly-Si film") thereon, and forming an oxidation resisting film thereon and performing thermal oxidation.
Now referring to the drawings, an explanation will be iven of a method of manufacturing a semiconductor device using the PBL technique.
STEP 1:
As seen from FIG. 3A, a pad oxide film 52 is formed on a semiconductor substrate 51 using the thermal oxidation technique. A pad poly-Si film 53 is formed on the pad oxide film 52 on the CVD (Chemical Vapor Deposition) technique. A silicon nitride film 54 serving as an oxidation resisting film is formed using the CVD technique to form an opening in the region where an element isolation film is to be formed.
STEP 2:
As seen from FIG. 3B, the semiconductor substrate 51 is thermally oxidized using the silicon nitride film 54 as a mask to form an element isolation film 55. At this time, the pad oxide film 52 prevents crystal defects on the surface of the semiconductor substrate beneath a bird's beak from occurring. The bird's beak may be generated in such a way that the oxide region of the semiconductor substrate 51 constituting the element isolation film 55 extends more externally than the edge of the opening of the mask and its tip intrudes leanly in between the silicon nitride film 54 and semiconductor substrate 51. The pad poly-Si film 53 suppresses the bird's beak from extending.
STEP 3:
As seen from FIG. 3C, the pad oxide film 52, pad poly-Si film 53 and silicon nitride film 54, which are located on the region where an element is formed, are removed.
STEP 4:
As seen from FIG. 3D, using the thermal oxidation technique, a gate insulating film 56 is formed, and using the CVD technique, a poly-Si film 57 and a tungsten silicide film 58 are formed.
STEP 5:
As seen from FIG. 3E, using the photolithography, the poly-Si film 57 and tungsten silicide film 58 are patterned to form a gate electrode 59 and wiring 60. Thereafter, using the gate electrode 59 as a mask, impurity ions are injected into the surface of the semiconductor substrate 51 using the ion implantation technique to form a source/drain region (not shown) Further, an interlayer insulating film and wiring are made, thereby completing a semiconductor integrated circuit.
As described above, when the element isolation film is formed using the LOCOS technique, the pad oxide film 52 and pad poly-Si film 53, which are left beneath the silicon nitride film 54 serving as an oxidation resisting film, serve as a buffer layer for suppressing the growth of the bird's beak. However, they are once removed in the manufacturing process and thereafter the gate insulating film 56 and the poly-Si film 57 constituting the gate electrode are stacked. This increases the number of the manufacturing steps. Further, the element isolation region 55 is formed to swell from the surface of the semiconductor substrate 1 so that a large level difference-is produced between the gate electrode 58 formed on the gate insulating film 56 and the wiring 60 formed on the element isolation film 55. Therefore, in the lithography process in the subsequent wiring forming step, the accuracy of adjusting a focal point for exposure is attenuated and hence sufficient pattern accuracy cannot be attained.